A widely used type of analog-to-digital converter is a so-called pipeline ADC. Taking a 12-bit pipeline ADC as an example, the 12-bit pipeline ADC comprises a sample-and-hold amplifier (SHA) for sampling an analog input and five pipeline stages, each of which generates digital bits corresponding to the amplitude of the analog input. Usually, the 12-bit ADC has an 8-level flash ADC connected in series with the stages. The five pipeline stages and the 8-level flash ADC pass outputs thereof to an error correction logic circuit to be combined in a shifting manner, and then a 12-bit digital output is generated accordingly.
Each pipeline stage of the pipeline ADC comprises a sub-ADC and a multiplying digital-to-analog converter (MDAC). The sub-ADC quantizes an analog input into a 3-bit output and passes the same to a sub-DAC of the MDAC. The output of the sub-DAC is subtracted from the analog input to obtain a difference. The difference is amplified by 4 times to generate a residue, which is passed to the next pipeline stage.
To add programmable gain function to the pipeline ADC, one method is to design an SHA with programmable gain function. Otherwise, an additional programmable gain amplification (PGA) stage is added in front of the SHA.
In some cases, such as low speed pipeline ADC designs, it is possible that the SHA is not used. Under such a condition, the pipeline ADC structure having an SHA with the programmable gain function cannot be implemented. In addition, it will be desirable if the PGA stage can be removed while the programmable gain function can be still provided.